Static Random Access Memory (SRAM) is a type of random access memory. The term ‘static’ differentiates it from Dynamic Random Access Memory (DRAM) which must be periodically refreshed. Data can be well maintained in a SRAM as long as the SRAM keeps powered. However, when the SRAM is cut off from power, the data stored therein will be lost. In comparison, a Read Only Memory (ROM) or a flash memory can still keep the data stored therein even when power is off.
FIG. 1 illustrates a circuit diagram of a 6T SRAM cell. Referring to FIG. 1, the 6T SRAM includes pull-up transistors PU1 and PU2, pull-down transistors PD1 and PD2, and pass gate transistors PG1 and PG2. The pull-up transistors PU1 and PU2 are P-Mental-Oxide-Semiconductor (PMOS) transistors, and the pull-down transistors PD1 and PD2 and the pass gate transistors PG1 and PG2 are N-Mental-Oxide-Semiconductor (NMOS) transistors. In FIG. 1, a word line WL, two source lines Vdd and Vss, and two bit lines BL and BLB are connected to the 6T SRAM cell. Data can be written to a node N1 and a node N2 by applying voltages to the word line WL and the bit lines BL and BLB.
Generally, write margin is used to indicate performance of a SRAM cell. Referring to FIG. 1, assume that in an original state, the node N1 is set at a high electrical level and stores data “1”, and the node N2 is set at a low electrical level and stores data “0”. Operations to write “0” into the node N1 and write “1” into the node N2 are illustrated as follows.
Before writing operation is initiated, the bit line BL is charged to a high electrical level and the bit line BLB is charged to a low electrical level. When the writing operation starts, a high voltage is applied to the word line WL to enable the pass gate transistors PG1 and PG2 in a conducting state. Since in the original state, the node N2 is set at the low electrical level to enable the pull-up transistor PU2 in a conducting state and enable the pull-down transistor PD2 in an off state, the pull-up transistor PU2 and the pass gate transistor PG2 are in a non-saturated conducting state at the beginning of the writing operation. Therefore, the node N1 changes from the high electrical level to a middle electrical level between the high electrical level and the low electrical level. The middle electrical level may depend on equivalent resistance of the pull-up transistor PU2 and the pass gate transistor PG2.
To write data, the value of the middle electrical level should be less than a predetermined value, i.e., a ratio of the equivalent resistance of the pass gate transistor PG2 to the equivalent resistance of the pull-up transistor PU2 should be less than the predetermined value. The smaller the value of the middle electrical level is, the greater the write margin of the SRAM shall be.
Nowadays, semiconductor devices are getting smaller while stress becomes more influential to device performance. Compressive stress can increase hole mobility of a PMOS transistor, and tensile stress can increase electron mobility of a NMOS transistor. In existing techniques, to improve performance of a SRAM cell, compressive stress films may be formed to cover the pull-up transistors in the SRAM cell, and tensile stress films may be formed to cover pull-down transistors and pass gate transistors in the SRAM cell.
However, although forming stress films covering transistors in a SRAM cell may improve its performance, it cannot increase write margin of the SRAM cell. Therefore, write margin of SRAM is relatively small in the existing techniques.